Available on AArch64 or
target_arch="arm64ec"
only.Expand description
Platform-specific intrinsics for the aarch64
platform.
See the module documentation for more details.
Structs§
- SYExperimentalFull system is the required shareability domain, reads and writes are the required access types
Constants§
- _PREFETCH_LOCALITY0ExperimentalSee
prefetch
. - _PREFETCH_LOCALITY1ExperimentalSee
prefetch
. - _PREFETCH_LOCALITY2ExperimentalSee
prefetch
. - _PREFETCH_LOCALITY3ExperimentalSee
prefetch
. - _PREFETCH_READExperimentalSee
prefetch
. - _PREFETCH_WRITEExperimentalSee
prefetch
. - _TMFAILURE_CNCLExperimentalTransaction executed a TCANCEL instruction
- _TMFAILURE_DBGExperimentalTransaction aborted due to a debug trap.
- _TMFAILURE_ERRExperimentalTransaction aborted because a non-permissible operation was attempted
- _TMFAILURE_IMPExperimentalFallback error type for any other reason
- _TMFAILURE_INTExperimentalTransaction failed from interrupt
- _TMFAILURE_MEMExperimentalTransaction aborted because a conflict occurred
- _TMFAILURE_NESTExperimentalTransaction aborted due to transactional nesting level was exceeded
- _TMFAILURE_REASONExperimentalExtraction mask for failure reason
- _TMFAILURE_RTRYExperimentalTransaction retry is possible.
- _TMFAILURE_SIZEExperimentalTransaction aborted due to read or write set limit was exceeded
- _TMFAILURE_TRIVIALExperimentalIndicates a TRIVIAL version of TM is available
- _TMSTART_SUCCESSExperimentalTransaction successfully started.
Functions§
- CRC32 single round checksum for bytes (8 bits).
- CRC32-C single round checksum for bytes (8 bits).
- CRC32-C single round checksum for half words (16 bits).
- CRC32-C single round checksum for words (32 bits).
- CRC32 single round checksum for half words (16 bits).
- CRC32 single round checksum for words (32 bits).
- __dmb⚠ExperimentalGenerates a DMB (data memory barrier) instruction or equivalent CP15 instruction.
- __dsb⚠ExperimentalGenerates a DSB (data synchronization barrier) instruction or equivalent CP15 instruction.
- __isb⚠ExperimentalGenerates an ISB (instruction synchronization barrier) instruction or equivalent CP15 instruction.
- __nop⚠ExperimentalGenerates an unspecified no-op instruction.
- __sev⚠ExperimentalGenerates a SEV (send a global event) hint instruction.
- __sevl⚠ExperimentalGenerates a send a local event hint instruction.
- Cancels the current transaction and discards all state modifications that were performed transactionally.
- Commits the current transaction. For a nested transaction, the only effect is that the transactional nesting depth is decreased. For an outer transaction, the state modifications performed transactionally are committed to the architectural state.
- Starts a new transaction. When the transaction starts successfully the return value is 0. If the transaction fails, all state modifications are discarded and a cause of the failure is encoded in the return value.
- Tests if executing inside a transaction. If no transaction is currently executing, the return value is 0. Otherwise, this intrinsic returns the depth of the transaction.
- __wfe⚠ExperimentalGenerates a WFE (wait for event) hint instruction, or nothing.
- __wfi⚠ExperimentalGenerates a WFI (wait for interrupt) hint instruction, or nothing.
- __yield⚠ExperimentalGenerates a YIELD hint instruction.
- _prefetch⚠ExperimentalFetch the cache line that contains address
p
using the givenRW
andLOCALITY
.