34 #ifndef _RTE_ETH_CTRL_H_ 35 #define _RTE_ETH_CTRL_H_ 59 #define RTE_ETH_FLOW_UNKNOWN 0 60 #define RTE_ETH_FLOW_RAW 1 61 #define RTE_ETH_FLOW_IPV4 2 62 #define RTE_ETH_FLOW_FRAG_IPV4 3 63 #define RTE_ETH_FLOW_NONFRAG_IPV4_TCP 4 64 #define RTE_ETH_FLOW_NONFRAG_IPV4_UDP 5 65 #define RTE_ETH_FLOW_NONFRAG_IPV4_SCTP 6 66 #define RTE_ETH_FLOW_NONFRAG_IPV4_OTHER 7 67 #define RTE_ETH_FLOW_IPV6 8 68 #define RTE_ETH_FLOW_FRAG_IPV6 9 69 #define RTE_ETH_FLOW_NONFRAG_IPV6_TCP 10 70 #define RTE_ETH_FLOW_NONFRAG_IPV6_UDP 11 71 #define RTE_ETH_FLOW_NONFRAG_IPV6_SCTP 12 72 #define RTE_ETH_FLOW_NONFRAG_IPV6_OTHER 13 73 #define RTE_ETH_FLOW_L2_PAYLOAD 14 74 #define RTE_ETH_FLOW_IPV6_EX 15 75 #define RTE_ETH_FLOW_IPV6_TCP_EX 16 76 #define RTE_ETH_FLOW_IPV6_UDP_EX 17 77 #define RTE_ETH_FLOW_MAX 18 83 RTE_ETH_FILTER_NONE = 0,
84 RTE_ETH_FILTER_MACVLAN,
85 RTE_ETH_FILTER_ETHERTYPE,
86 RTE_ETH_FILTER_FLEXIBLE,
88 RTE_ETH_FILTER_NTUPLE,
89 RTE_ETH_FILTER_TUNNEL,
109 RTE_ETH_FILTER_OP_MAX
137 #define RTE_ETHTYPE_FLAGS_MAC 0x0001 138 #define RTE_ETHTYPE_FLAGS_DROP 0x0002 145 struct rte_eth_ethertype_filter { 152 #define RTE_FLEX_FILTER_MAXLEN 128 153 #define RTE_FLEX_FILTER_MASK_SIZE \ 154 (RTE_ALIGN(RTE_FLEX_FILTER_MAXLEN, CHAR_BIT) / CHAR_BIT) 186 #define RTE_NTUPLE_FLAGS_DST_IP 0x0001 187 #define RTE_NTUPLE_FLAGS_SRC_IP 0x0002 188 #define RTE_NTUPLE_FLAGS_DST_PORT 0x0004 189 #define RTE_NTUPLE_FLAGS_SRC_PORT 0x0008 190 #define RTE_NTUPLE_FLAGS_PROTO 0x0010 191 #define RTE_NTUPLE_FLAGS_TCP_FLAG 0x0020 193 #define RTE_5TUPLE_FLAGS ( \ 194 RTE_NTUPLE_FLAGS_DST_IP | \ 195 RTE_NTUPLE_FLAGS_SRC_IP | \ 196 RTE_NTUPLE_FLAGS_DST_PORT | \ 197 RTE_NTUPLE_FLAGS_SRC_PORT | \ 198 RTE_NTUPLE_FLAGS_PROTO) 200 #define RTE_2TUPLE_FLAGS ( \ 201 RTE_NTUPLE_FLAGS_DST_PORT | \ 202 RTE_NTUPLE_FLAGS_PROTO) 204 #define TCP_URG_FLAG 0x20 205 #define TCP_ACK_FLAG 0x10 206 #define TCP_PSH_FLAG 0x08 207 #define TCP_RST_FLAG 0x04 208 #define TCP_SYN_FLAG 0x02 209 #define TCP_FIN_FLAG 0x01 210 #define TCP_FLAG_ALL 0x3F 242 RTE_TUNNEL_TYPE_NONE = 0,
243 RTE_TUNNEL_TYPE_VXLAN,
244 RTE_TUNNEL_TYPE_GENEVE,
245 RTE_TUNNEL_TYPE_TEREDO,
246 RTE_TUNNEL_TYPE_NVGRE,
253 #define ETH_TUNNEL_FILTER_OMAC 0x01 254 #define ETH_TUNNEL_FILTER_OIP 0x02 255 #define ETH_TUNNEL_FILTER_TENID 0x04 256 #define ETH_TUNNEL_FILTER_IMAC 0x08 257 #define ETH_TUNNEL_FILTER_IVLAN 0x10 258 #define ETH_TUNNEL_FILTER_IIP 0x20 260 #define RTE_TUNNEL_FILTER_IMAC_IVLAN (ETH_TUNNEL_FILTER_IMAC | \ 261 ETH_TUNNEL_FILTER_IVLAN) 262 #define RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID (ETH_TUNNEL_FILTER_IMAC | \ 263 ETH_TUNNEL_FILTER_IVLAN | \ 264 ETH_TUNNEL_FILTER_TENID) 265 #define RTE_TUNNEL_FILTER_IMAC_TENID (ETH_TUNNEL_FILTER_IMAC | \ 266 ETH_TUNNEL_FILTER_TENID) 267 #define RTE_TUNNEL_FILTER_OMAC_TENID_IMAC (ETH_TUNNEL_FILTER_OMAC | \ 268 ETH_TUNNEL_FILTER_TENID | \ 269 ETH_TUNNEL_FILTER_IMAC) 289 uint32_t ipv6_addr[4];
302 RTE_ETH_GLOBAL_CFG_TYPE_UNKNOWN = 0,
303 RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN,
304 RTE_ETH_GLOBAL_CFG_TYPE_MAX,
318 #define RTE_ETH_FDIR_MAX_FLEXLEN 16 319 #define RTE_ETH_INSET_SIZE_MAX 128 324 enum rte_eth_input_set_field { 325 RTE_ETH_INPUT_SET_UNKNOWN = 0,
328 RTE_ETH_INPUT_SET_L2_SRC_MAC = 1,
329 RTE_ETH_INPUT_SET_L2_DST_MAC,
330 RTE_ETH_INPUT_SET_L2_OUTER_VLAN,
331 RTE_ETH_INPUT_SET_L2_INNER_VLAN,
332 RTE_ETH_INPUT_SET_L2_ETHERTYPE,
335 RTE_ETH_INPUT_SET_L3_SRC_IP4 = 129,
336 RTE_ETH_INPUT_SET_L3_DST_IP4,
337 RTE_ETH_INPUT_SET_L3_SRC_IP6,
338 RTE_ETH_INPUT_SET_L3_DST_IP6,
339 RTE_ETH_INPUT_SET_L3_IP4_TOS,
340 RTE_ETH_INPUT_SET_L3_IP4_PROTO,
341 RTE_ETH_INPUT_SET_L3_IP6_TC,
342 RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
345 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT = 257,
346 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT,
347 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT,
348 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT,
349 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT,
350 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT,
351 RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
354 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC = 385,
355 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_SRC_MAC,
356 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
357 RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
358 RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY,
361 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD = 641,
362 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
363 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
364 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
365 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
366 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
367 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
368 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
370 RTE_ETH_INPUT_SET_DEFAULT = 65533,
371 RTE_ETH_INPUT_SET_NONE = 65534,
372 RTE_ETH_INPUT_SET_MAX = 65535,
379 RTE_ETH_INPUT_SET_OP_UNKNOWN,
382 RTE_ETH_INPUT_SET_OP_MAX
487 RTE_FDIR_TUNNEL_TYPE_UNKNOWN = 0,
488 RTE_FDIR_TUNNEL_TYPE_NVGRE,
489 RTE_FDIR_TUNNEL_TYPE_VXLAN,
545 RTE_ETH_FDIR_ACCEPT = 0,
547 RTE_ETH_FDIR_PASSTHRU,
591 uint16_t vlan_tci_mask;
594 uint16_t src_port_mask;
595 uint16_t dst_port_mask;
596 uint8_t mac_addr_byte_mask;
605 RTE_ETH_PAYLOAD_UNKNOWN = 0,
610 RTE_ETH_PAYLOAD_MAX = 8,
660 #define UINT32_BIT (CHAR_BIT * sizeof(uint32_t)) 661 #define RTE_FLOW_MASK_ARRAY_SIZE \ 662 (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT32_BIT)/UINT32_BIT) 679 uint32_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE];
721 RTE_ETH_FDIR_FILTER_INFO_TYPE_UNKNOWN = 0,
724 RTE_ETH_FDIR_FILTER_INFO_TYPE_MAX,
751 RTE_ETH_HASH_FILTER_INFO_TYPE_UNKNOWN = 0,
758 RTE_ETH_HASH_FILTER_INFO_TYPE_MAX,
765 RTE_ETH_HASH_FUNCTION_DEFAULT = 0,
768 RTE_ETH_HASH_FUNCTION_MAX,
771 #define RTE_SYM_HASH_MASK_ARRAY_SIZE \ 772 (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT32_BIT)/UINT32_BIT) 785 uint32_t sym_hash_enable_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
787 uint32_t valid_bit_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
#define RTE_ETH_FDIR_MAX_FLEXLEN
uint32_t flex_payload_unit
rte_eth_fdir_filter_info_type
#define RTE_FLEX_FILTER_MAXLEN
uint32_t max_flex_payload_segment_num
struct ether_addr * inner_mac
uint32_t max_flex_bitmask_num
struct ether_addr * outer_mac
uint32_t flex_bitmask_unit
enum rte_mac_filter_type filter_type
uint16_t flex_payload_limit
#define RTE_ETH_INSET_SIZE_MAX
#define RTE_FLEX_FILTER_MASK_SIZE
rte_eth_hash_filter_info_type