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oMan PageContent-type: text/html; charset=UTF-8 Man page of VRQ

VRQ

Section: User Commands (1)
Updated: November 2016
Index Return to Main Contents
 

NAME

Vrq - manual page for Vrq 1.0.127,  

SYNOPSIS

vrq [options] <file1> [<file2>...]  

DESCRIPTION

'Vrq' is a framework for creating verilog based tools.  

OPTIONS

--version
Print version
--help
This message
--bindir
Binary install path
--libdir
Library install path
--pkglibdir
Plugin install path
--includedir
Include install path
--cflags
Compiler flags used
--ldflags
Linker flags used
--libs
Libraries used
--randomizeheap
Randomize heap
-V
Verbose
-y <directory>
Search directory for module definitions
-f <filename>
Read options from <filename>
-v <lib_filename>
Search file for module definitions
-l <filename>
Set log file to <filename>
-w <message>=<policy>
Set policy for warning <message> to <policy>; ignore, warning, error, info
-w all=<policy>
Set policy for all warnings to <policy>; ignore, warning, error, info
-wl
List all warning messages
+libext+<extension>
Specify library suffix to <extension>
-sv
Enable System Verilog support
-dump
Dump internal tree
-debug
Print debug/statistics info
-quiet
Print minimal runtime info
-lexbuffersize <bufferSize> Set lexer buffer size (default=1048576)
-infervectors
Infer reg and wire vectors
-keeptickdefines
Best effort attempt to keep tick defines and `include statements in code (EXPERIMENTAL)
-macrocheck
Do not allow undefined macros
-o <filename>
Specify output file
-dir <directory>
Specify output directory
-pragma <regexp>
Extended regular expression template for pragma comments
-passthru <name>
Pass through ifdef blocks with label
+incdir+<directory>
Specify include search path
+define+<name>=<value>
Define `define
+<name>+<value>
Define plusargs
-tool builder
Auto route hierarchy
-tool coverage
Add line coverage instrumentation
-tool dump
Print verilog output
-tool filter
Extract elements of hierarchy
-tool flatten
Reduce to single level hiearchy
-tool rectify
Replace all X constants with 0 or 1
-tool sim
Verilog simulator
-tool stats
Print summary of hiearchy
-tool xprop
Add X propagation instrumentation

* 'builder' Options

+tree_ext=<ext>
File extension for files to be expanded
+depend=<filename>
Generate dependency info
+builder-verbose
Dump vebose log of actions

* 'coverage' Options

+coverage_output_file=<filename> Filename for coverage line mapping info

* 'dump' Options

+dump-alt-rxnor
Use alternate rxnor op ^~
+dump-fps
Force part selects on all vectors
+dump-fvl
Convert all logical ops to vector ops
+dump-fcc
Convert all comments to c++ style
+dump-swda
Split wire declaration assignments
+dump-fbae
Force begin/end block after event statement
+dump-nns
Replace null statements with begin/end pairs
+dump-sabo
Add spaces around binary operators
+dump-ced
Create explicit declarations for implicitly declared variables
+dump-strip-attr
strip out all attributes
+dump-timescale=<timescale> emit `timescale <timescale> statements for all modules missing `timescale declarations
+dump-simplify
Simplify constant expressions (EXPERIMENTAL)

* 'filter' Options

+filter-default-policy-keep keep all element by default
+filter-default-policy-delete delete all element by default (tool default behavior)
+filter-comment-keep
keep comment
+filter-comment-delete
delete comment
+filter-vrq-keep
keep vrq comment
+filter-vrq-delete
delete vrq comment
+filter-pragma-keep
keep program pragma
+filter-pragma-delete
delete program pragma
+filter-instance-ref-keep
keep instance reference
+filter-instance-ref-delete delete instance reference
+filter-gate-ref-keep
keep gate instance
+filter-gate-ref-delete
delete gate instance
+filter-task-enable-keep
keep call to a task
+filter-task-enable-delete delete call to a task
+filter-systask-call-keep
keep call to enable a systask
+filter-systask-call-delete delete call to enable a systask
+filter-timing-call-keep
keep call to a timing task
+filter-timing-call-delete delete call to a timing task
+filter-function-call-keep keep call to a function
+filter-function-call-delete delete call to a function
+filter-enum-ref-keep
keep reference to a enum
+filter-enum-ref-delete
delete reference to a enum
+filter-type-ref-keep
keep reference to a type
+filter-type-ref-delete
delete reference to a type
+filter-net-decl-keep
keep net declaration
+filter-net-decl-delete
delete net declaration
+filter-var-decl-keep
keep variable declaration
+filter-var-decl-delete
delete variable declaration
+filter-param-decl-keep
keep parameter declaration
+filter-param-decl-delete
delete parameter declaration
+filter-specparam-decl-keep keep specify parameter declaration
+filter-specparam-decl-delete delete specify parameter declaration
+filter-port-decl-keep
keep port declaration
+filter-port-decl-delete
delete port declaration
+filter-genvar-decl-keep
keep genvar declaration
+filter-genvar-decl-delete delete genvar declaration
+filter-typedef-decl-keep
keep type declaration
+filter-typedef-decl-delete delete type declaration
+filter-init-keep
keep initial block
+filter-init-delete
delete initial block
+filter-always-keep
keep always block
+filter-always-delete
delete always block
+filter-always-latch-keep
keep always latch block
+filter-always-latch-delete delete always latch block
+filter-always-ff-keep
keep always flip-flop block
+filter-always-ff-delete
delete always flip-flop block
+filter-always-comb-keep
keep always combinational logic block
+filter-always-comb-delete delete always combinational logic block
+filter-specify-ref-keep
keep specify block
+filter-specify-ref-delete delete specify block
+filter-assign-keep
keep procedural assignment
+filter-assign-delete
delete procedural assignment
+filter-gassign-keep
keep generate intialize assignment
+filter-gassign-delete
delete generate intialize assignment
+filter-add-assign-keep
keep procedural assignment with add
+filter-add-assign-delete
delete procedural assignment with add
+filter-sub-assign-keep
keep procedural assignment with subtract
+filter-sub-assign-delete
delete procedural assignment with subtract
+filter-mul-assign-keep
keep procedural assignment with mul
+filter-mul-assign-delete
delete procedural assignment with mul
+filter-div-assign-keep
keep procedural assignment with div
+filter-div-assign-delete
delete procedural assignment with div
+filter-mod-assign-keep
keep procedural assignment with mod
+filter-mod-assign-delete
delete procedural assignment with mod
+filter-and-assign-keep
keep procedural assignment with bitwise and
+filter-and-assign-delete
delete procedural assignment with bitwise and
+filter-or-assign-keep
keep procedural assignment with bitwise or
+filter-or-assign-delete
delete procedural assignment with bitwise or
+filter-xor-assign-keep
keep procedural assignment with bitwise xor
+filter-xor-assign-delete
delete procedural assignment with bitwise xor
+filter-lsh-assign-keep
keep procedural assignment with left shift
+filter-lsh-assign-delete
delete procedural assignment with left shift
+filter-rsh-assign-keep
keep procedural assignment with right shift
+filter-rsh-assign-delete
delete procedural assignment with right shift
+filter-lsha-assign-keep
keep procedural assignment with left arithmetic shift
+filter-lsha-assign-delete delete procedural assignment with left arithmetic shift
+filter-rsha-assign-keep
keep procedural assignment with right arithmetic shift
+filter-rsha-assign-delete delete procedural assignment with right arithmetic shift
+filter-force-keep
keep force statement
+filter-force-delete
delete force statement
+filter-release-keep
keep release statement
+filter-release-delete
delete release statement
+filter-nbassign-keep
keep nonblocking assignment
+filter-nbassign-delete
delete nonblocking assignment
+filter-if-keep
keep if statement
+filter-if-delete
delete if statement
+filter-forever-keep
keep forever statement
+filter-forever-delete
delete forever statement
+filter-repeat-keep
keep repeat statement
+filter-repeat-delete
delete repeat statement
+filter-while-keep
keep while statement
+filter-while-delete
delete while statement
+filter-wait-keep
keep wait statement
+filter-wait-delete
delete wait statement
+filter-for-keep
keep for statement
+filter-for-delete
delete for statement
+filter-case-keep
keep case statement
+filter-case-delete
delete case statement
+filter-casex-keep
keep casex statement
+filter-casex-delete
delete casex statement
+filter-casez-keep
keep casez statement
+filter-casez-delete
delete casez statement
+filter-cassign-keep
keep continious assignment
+filter-cassign-delete
delete continious assignment
+filter-import-keep
keep import item
+filter-import-delete
delete import item
+filter-function-def-keep
keep function definition
+filter-function-def-delete delete function definition
+filter-module-def-keep
keep module definition
+filter-module-def-delete
delete module definition
+filter-package-def-keep
keep package definition
+filter-package-def-delete delete package definition
+filter-port-def-keep
keep port definition
+filter-port-def-delete
delete port definition
+filter-defparam-keep
keep defparam statement
+filter-defparam-delete
delete defparam statement
+filter-path-keep
keep path statement
+filter-path-delete
delete path statement
+filter-trigger-keep
keep event trigger
+filter-trigger-delete
delete event trigger
+filter-passign-keep
keep procedural assignment
+filter-passign-delete
delete procedural assignment
+filter-deassign-keep
keep deassign statement
+filter-deassign-delete
delete deassign statement
+filter-disable-keep
keep disable statement
+filter-disable-delete
delete disable statement
+filter-attribute-keep
keep attribute specification
+filter-attribute-delete
delete attribute specification
+filter-gif-keep
keep structural if statement
+filter-gif-delete
delete structural if statement
+filter-gfor-keep
keep structural for statement
+filter-gfor-delete
delete structural for statement
+filter-gcase-keep
keep structural case statement
+filter-gcase-delete
delete structural case statement
+filter-table-keep
keep udp table
+filter-table-delete
delete udp table
+filter-enum-spec-keep
keep enum specification
+filter-enum-spec-delete
delete enum specification
+filter-member-keep
keep member reference (structure, class or external
+filter-member-delete
delete member reference (structure, class or external
+filter-return-keep
keep return
+filter-return-delete
delete return
+filter-preinc-keep
keep preincrement
+filter-preinc-delete
delete preincrement
+filter-postinc-keep
keep postincrement
+filter-postinc-delete
delete postincrement
+filter-predec-keep
keep predecrement
+filter-predec-delete
delete predecrement
+filter-postdec-keep
keep postdecrement
+filter-postdec-delete
delete postdecrement
+filter-cast-keep
keep data type change
+filter-cast-delete
delete data type change
+filter-assignment-pattern-keep keep assignment_pattern
+filter-assignment-pattern-delete delete assignment_pattern
+filter-dollar-keep
keep queue dimension
+filter-dollar-delete
delete queue dimension

* 'rectify' Options

+rectify-default-value={0|1} change default replacement value
+rectify-attribute-name=<attrName> attribute name used to override default replacement value
+rectify-delete-decl-pragmas delete pragmas attached to declarations

* 'sim' Options

+sim-interactive
start simulation in interactive mode only
+sim-compile-only
do not simulate, compile only
+sim-trace
enable execution tracing
+sim-mindelays
use minimum delays
+sim-typdelays
use typical delays
+sim-maxdelays
use maximum delays
+sim-pli=pliLib1+pliLib2+... load pli librarys
+sim-log=file
use file for logging
+sim-key=file
use file for key stroke log

* 'xprop' Options

+xprop-begin=<pragma>
insertion begin pragma
+xprop-end=<pragma>
insertion end pragma
+xprop-clk-begin=<pragma>
insertion clock begin pragma
+xprop-clk-end=<pragma>
insertion clock end pragma
+xprop-disable-task
disable task output instrumentation
+xprop-disable-if
disable if instrumentation
+xprop-disable-case
disable case instrumentation
+xprop-disable-index
disable reference instrumentation
+xprop-disable-ternary
disable '?' instrumentation
+xprop-nox-attr=<name>
attribute specifing variable will never be x
+xprop-int-nox
declare integers will never be x
+xprop-enable-clock
instrument register clocks
+xprop-clk-edge-control=[!]<tickdefine> Supply a preprocessor tick define to enable instrumentation on both edges of the clock. ! indicates tickdefine disables both edges. If switch isn't supplied the behavior is single edge unless XPROP_BOTH_EDGES is defined
 

AUTHOR

Written by Mark Hummel  

REPORTING BUGS

Report bugs at <http://sourceforge.net/projects/vrq>  

COPYRIGHT

Copyright © 1997-2009 Mark Hummel

Vrq comes with ABSOLUTELY NO WARRANTY; This is free software, and you are welcome to redistribute it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.


 

Index

NAME
SYNOPSIS
DESCRIPTION
OPTIONS
AUTHOR
REPORTING BUGS
COPYRIGHT

This document was created by man2html, using the manual pages.
Time: 21:04:44 GMT, November 22, 2016
oFrequently Asked Questions vrq » vrqfaq

Frequently Asked Questions

What license is VRQ released under?

VRQ is released under the GPLv2 license. Currently all the include plugins are GPLv2 as well, however this many not remain the case as any compatible license would be allowed.

Does that prohibit me from using verilog code processed by VRQ in commercial products?

Absolutely not! The intent is provide a useful tool an framework the all may to create HW for commercial, educational or personal benefit.

Can the VRQ lex, parser, etc be included in a commercial SW product?

No VRQ is released under the GPLv2 license and its terms of use must be met. However it is possible to supply VRQ under a different license, please contact the author for details.

Can I write a plugin tool? Is there documentation available regarding the tool API and VRQ internals?

You can certainly write a tool, there have been others who have. However at this time there is no documentation other than the source code to help with this. If you wish to do so the file node.h contains the parse tree node descriptions. Also using one of the existing plugin tools as a template can be most helpful.

Does VRQ support the entire Verilog 2005 standard?

Not completely. There are a few small things like the library constructs that are not currently supported. Note however some of the tools are less complete. For instance the sim tool is based upon the VeriWell source code which only supports a subset of Verilog 1995.

Does VRQ support System Verilog? If not will it in the future?

Currently VRQ does not support System Verilog constructs. Over time support will be added.

Can the output of one tool be used as the input to another?

Yes. You can use multiple -tool switches on the command line. The output of one tool will be pipelined into the input of the next.

oPlugin List
oQuick Start
oHow to Build a PluginVrq plugins are independently compiled as standalone DLLs
oExample PluginThis example plugin searches the parsed code and finds register and net declarations and references
oExample PluginThis example plugin converts all procedural if statements to case statements
oDump PluginThe dump tool emits the parsed and processed parse trees back in to verilog
oXprop ToolThe xprop tool is specified using the -tool xprop switch on the command line
oXprop RationalXprop is a tool that instruments verilog code such that x's are propagated and not squashed
oParse Tree NodesList of all parse tree nodes
oFilter PluginThe filter tool edits the parse trees, selectively deleting nodes based on a filter specification that is supplied by command line switches
oRectify PluginThe rectify tool edits the parse trees replacing 'x' bits in constants with a default value of 0 or 1
\Todo List