Intel(R) Threading Building Blocks Doxygen Documentation  version 4.2.3
msvc_armv7.h
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1 /*
2  Copyright (c) 2005-2019 Intel Corporation
3 
4  Licensed under the Apache License, Version 2.0 (the "License");
5  you may not use this file except in compliance with the License.
6  You may obtain a copy of the License at
7 
8  http://www.apache.org/licenses/LICENSE-2.0
9 
10  Unless required by applicable law or agreed to in writing, software
11  distributed under the License is distributed on an "AS IS" BASIS,
12  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  See the License for the specific language governing permissions and
14  limitations under the License.
15 
16 
17 
18 
19 */
20 
21 #if !defined(__TBB_machine_H) || defined(__TBB_msvc_armv7_H)
22 #error Do not #include this internal file directly; use public TBB headers instead.
23 #endif
24 
25 #define __TBB_msvc_armv7_H
26 
27 #include <intrin.h>
28 #include <float.h>
29 
30 #define __TBB_WORDSIZE 4
31 
32 #define __TBB_ENDIANNESS __TBB_ENDIAN_UNSUPPORTED
33 
34 #if defined(TBB_WIN32_USE_CL_BUILTINS)
35 // We can test this on _M_IX86
36 #pragma intrinsic(_ReadWriteBarrier)
37 #pragma intrinsic(_mm_mfence)
38 #define __TBB_compiler_fence() _ReadWriteBarrier()
39 #define __TBB_full_memory_fence() _mm_mfence()
40 #define __TBB_control_consistency_helper() __TBB_compiler_fence()
41 #define __TBB_acquire_consistency_helper() __TBB_compiler_fence()
42 #define __TBB_release_consistency_helper() __TBB_compiler_fence()
43 #else
44 //Now __dmb(_ARM_BARRIER_SY) is used for both compiler and memory fences
45 //This might be changed later after testing
46 #define __TBB_compiler_fence() __dmb(_ARM_BARRIER_SY)
47 #define __TBB_full_memory_fence() __dmb(_ARM_BARRIER_SY)
48 #define __TBB_control_consistency_helper() __TBB_compiler_fence()
49 #define __TBB_acquire_consistency_helper() __TBB_full_memory_fence()
50 #define __TBB_release_consistency_helper() __TBB_full_memory_fence()
51 #endif
52 
53 //--------------------------------------------------
54 // Compare and swap
55 //--------------------------------------------------
56 
65 #define __TBB_MACHINE_DEFINE_ATOMICS_CMPSWP(S,T,F) \
66 inline T __TBB_machine_cmpswp##S( volatile void *ptr, T value, T comparand ) { \
67  return _InterlockedCompareExchange##F(reinterpret_cast<volatile T *>(ptr),value,comparand); \
68 } \
69 
70 #define __TBB_MACHINE_DEFINE_ATOMICS_FETCHADD(S,T,F) \
71 inline T __TBB_machine_fetchadd##S( volatile void *ptr, T value ) { \
72  return _InterlockedExchangeAdd##F(reinterpret_cast<volatile T *>(ptr),value); \
73 } \
74 
80 #if defined(TBB_WIN32_USE_CL_BUILTINS)
81 // No _InterlockedExchangeAdd64 intrinsic on _M_IX86
82 #define __TBB_64BIT_ATOMICS 0
83 #else
85 #endif
86 
87 inline void __TBB_machine_pause (int32_t delay )
88 {
89  while(delay>0)
90  {
92  delay--;
93  }
94 }
95 
96 // API to retrieve/update FPU control setting
97 #define __TBB_CPU_CTL_ENV_PRESENT 1
98 
99 namespace tbb {
100 namespace internal {
101 
102 template <typename T, size_t S>
103 struct machine_load_store_relaxed {
104  static inline T load ( const volatile T& location ) {
105  const T value = location;
106 
107  /*
108  * An extra memory barrier is required for errata #761319
109  * Please see http://infocenter.arm.com/help/topic/com.arm.doc.uan0004a
110  */
112  return value;
113  }
114 
115  static inline void store ( volatile T& location, T value ) {
116  location = value;
117  }
118 };
119 
120 class cpu_ctl_env {
121 private:
122  unsigned int my_ctl;
123 public:
124  bool operator!=( const cpu_ctl_env& ctl ) const { return my_ctl != ctl.my_ctl; }
125  void get_env() { my_ctl = _control87(0, 0); }
126  void set_env() const { _control87( my_ctl, ~0U ); }
127 };
128 
129 } // namespace internal
130 } // namespaces tbb
131 
132 // Machine specific atomic operations
133 #define __TBB_CompareAndSwap4(P,V,C) __TBB_machine_cmpswp4(P,V,C)
134 #define __TBB_CompareAndSwap8(P,V,C) __TBB_machine_cmpswp8(P,V,C)
135 #define __TBB_Pause(V) __TBB_machine_pause(V)
136 
137 // Use generics for some things
138 #define __TBB_USE_FETCHSTORE_AS_FULL_FENCED_STORE 1
139 #define __TBB_USE_GENERIC_HALF_FENCED_LOAD_STORE 1
140 #define __TBB_USE_GENERIC_PART_WORD_FETCH_ADD 1
141 #define __TBB_USE_GENERIC_PART_WORD_FETCH_STORE 1
142 #define __TBB_USE_GENERIC_FETCH_STORE 1
143 #define __TBB_USE_GENERIC_DWORD_LOAD_STORE 1
144 #define __TBB_USE_GENERIC_SEQUENTIAL_CONSISTENCY_LOAD_STORE 1
145 
146 #if defined(TBB_WIN32_USE_CL_BUILTINS)
147 #if !__TBB_WIN8UI_SUPPORT
148 extern "C" __declspec(dllimport) int __stdcall SwitchToThread( void );
149 #define __TBB_Yield() SwitchToThread()
150 #else
151 #include<thread>
152 #define __TBB_Yield() std::this_thread::yield()
153 #endif
154 #else
155 #define __TBB_Yield() __yield()
156 #endif
157 
158 // Machine specific atomic operations
159 #define __TBB_AtomicOR(P,V) __TBB_machine_OR(P,V)
160 #define __TBB_AtomicAND(P,V) __TBB_machine_AND(P,V)
161 
162 template <typename T1,typename T2>
163 inline void __TBB_machine_OR( T1 *operand, T2 addend ) {
164  _InterlockedOr((long volatile *)operand, (long)addend);
165 }
166 
167 template <typename T1,typename T2>
168 inline void __TBB_machine_AND( T1 *operand, T2 addend ) {
169  _InterlockedAnd((long volatile *)operand, (long)addend);
170 }
171 
#define __TBB_MACHINE_DEFINE_ATOMICS_FETCHADD(S, T, F)
Definition: msvc_armv7.h:70
#define __TBB_MACHINE_DEFINE_ATOMICS_CMPSWP(S, T, F)
Definition: msvc_armv7.h:65
static void store(volatile T &location, T value)
Definition: msvc_armv7.h:115
void __TBB_machine_AND(T1 *operand, T2 addend)
Definition: msvc_armv7.h:168
The graph class.
bool operator!=(const cpu_ctl_env &ctl) const
Definition: msvc_armv7.h:124
__declspec(dllimport) int __stdcall SwitchToThread(void)
void const char const char int ITT_FORMAT __itt_group_sync x void const char ITT_FORMAT __itt_group_sync s void ITT_FORMAT __itt_group_sync p void ITT_FORMAT p void ITT_FORMAT p no args __itt_suppress_mode_t unsigned int void size_t ITT_FORMAT d void ITT_FORMAT p void ITT_FORMAT p __itt_model_site __itt_model_site_instance ITT_FORMAT p __itt_model_task __itt_model_task_instance ITT_FORMAT p void ITT_FORMAT p void ITT_FORMAT p void size_t ITT_FORMAT d void ITT_FORMAT p const wchar_t ITT_FORMAT s const char ITT_FORMAT s const char ITT_FORMAT s const char ITT_FORMAT s no args void ITT_FORMAT p size_t ITT_FORMAT d no args const wchar_t const wchar_t ITT_FORMAT s __itt_heap_function void size_t int ITT_FORMAT d __itt_heap_function void ITT_FORMAT p __itt_heap_function void void size_t int ITT_FORMAT d no args no args unsigned int ITT_FORMAT u const __itt_domain __itt_id ITT_FORMAT lu const __itt_domain __itt_id __itt_id __itt_string_handle ITT_FORMAT p const __itt_domain __itt_id ITT_FORMAT p const __itt_domain __itt_id __itt_timestamp __itt_timestamp ITT_FORMAT lu const __itt_domain __itt_id __itt_id __itt_string_handle ITT_FORMAT p const __itt_domain ITT_FORMAT p const __itt_domain __itt_string_handle unsigned long long value
void __TBB_machine_pause(int32_t delay)
Definition: msvc_armv7.h:87
void __TBB_machine_OR(T1 *operand, T2 addend)
Definition: msvc_armv7.h:163
#define __TBB_compiler_fence()
Definition: msvc_armv7.h:46
static T load(const volatile T &location)
Definition: msvc_armv7.h:104
#define __TBB_acquire_consistency_helper()
Definition: msvc_armv7.h:49

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